1. Field of the Invention
The present invention relates to a voltage comparator and, more particularly, to a Schmitt voltage comparator.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional Schmitt voltage comparator. Referring to FIG. 1, reference symbols Q1 and Q2 denote pnp transistors constituting a pair of differential amplifiers emitters of which are commonly connected to each other. Reference numeral 11 denotes a first constant current source connected between a power source having a voltage V.sub.CC and the common connection point of the emitters of the transistors Q1 and Q2. Reference symbol Q3 denotes an npn transistor a collector and an emitter of which are connected between the collector of the transistor Q1 and a ground voltage GND and a collector and a base of which are connected to each other. Reference symbol Q4 denotes an npn transistor a collector and an emitter of which are connected between the collector of the transistor Q2 and the GND and a base of which is connected to the base of the transistor Q3. Reference symbols R1 to R3 denote resistors connected in series between a power source having a reference voltage V.sub.REF and a power source having the ground voltage GND. The series connection point of the resistors R1 and R2 is connected to the base of the transistor Q1 as one of the transistors Q1 and Q2. Reference symbol Q5 is an npn transistor a base of which is connected to the collector of the transistor Q4 and an emitter of which is connected to the GND. Reference numeral 12 denotes a second constant current source connected between the power source having the voltage V.sub.CC and the collector of the transistor Q5. Reference symbol Q6 denotes an npn transistor a base of which is connected to the collector of the transistor Q5 and an emitter of which is connected to the power source of GND. Reference symbol R4 denotes a resistor connected between the power source having the voltage V.sub.CC and the collector of the transistor Q6. Reference symbol Q7 denotes an npn bias switching transistor a collector of which is connected to the series connection point of the resistors R2 and R3, an emitter of which is connected to the ground voltage of GND, and a base of which is connected to the base of the transistor Q6. An output voltage V.sub.OUT is extracted from the collector of the transistor Q6.
In the above voltage comparator, a threshold level V.sub.THU of an input voltage V.sub.IN at a rise time applied to the base of the other transistor Q2 selected from the transistors Q1 and Q2 is expressed by the following equation: ##EQU1##
A threshold level V.sub.THD of the input voltage V.sub.IN at a fall time is expressed by the following equation: ##EQU2## where R.sub.SAT denotes an ON resistance (collector-emitter saturation resistance) of the bias switching transistor Q7 and R3//R.sub.SAT denotes a resistance of the resistors R3 and R.sub.SAT. Since the resistance of the resistor R.sub.SAT is very low, equation 2 can be simplified as follows. ##EQU3## Therefore, a Schmitt width is defined by a voltage width between the voltages V.sub.THU and V.sub.REF.
However, in order to decrease the Schmitt width, a term including the resistance R.sub.SAT always has an error, and this error cannot be neglected. Design for the circuit becomes difficult.